1. Field of the Invention
The present invention relates to differential signal interfaces, and in particular, to low voltage differential signal transmitters for operating with low power dissipation.
2. Related Art
Differential input/output (I/O) signal interfaces are widely used for reliable high speed data transfer in many forms of data communication channels. They are used in both source synchronous and asynchronous communication systems. They can be used with bandwidth extension techniques, such as equalization and pre-emphasis. As is well known, differential signaling is preferred to single ended signaling due to its highly robust resistance to common mode noise associated with both conducted and radiated electromagnetic interference (EMI), as well as lower power dissipation compared to single ended static complementary metal oxide semiconductor (CMOS) implementations. Further, differential signaling also produces lower EMI emissions then their single ended counterparts due to reduced signal magnitudes and switching currents.
Referring to FIG. 1, a typical low voltage differential signal (LVDS) transmission circuit 10a includes switching transistors N1, P1, P2, N2 biased by an upper current source IBIAS1 and lower current source IBIAS2, all interconnected substantially as shown and biased by a power supply voltage VDD. (Throughout the following discussion, switching devices N1, P1, P2 and N2 are referred to as “transistors” since such devices are often implemented as pass transistors, with N1 and N2 are being N-type CMOS field effect transistors (CMOSFETs), and P1 and P2 being P-type CMOSFETs. However, as will be readily understood, as an alternative, the switching devices N1, P1, P2, N2 be either all N-type or all P-type transistors. Further, as yet another alternative, each of the switching devices N1, P1, P2, N2 can be implemented as a pair of complementary transistors, i.e., an N-type and a P-type together, coupled in parallel in what is known as a transmission gate.) Transistors N1 and N2 are turned on by the positive phase D of the differential data signal, while transistors P1 and P2 are turned on by the negative phase /D of the differential data signal. The differential output signal is conveyed via transmission lines (e.g., having a characteristics impedance of 50 ohms) which are terminated by a load resistance RL (e.g., typically having a real impedance of 100 ohms). Additionally, many implementations include an internal, or source, resistive termination RS (e.g., having a real impedance of 100 ohms).
One disadvantage of such a transmission circuit 10a is relatively high signal power consumption, particularly when the source termination RS is included. For example, a typical signal link biased with a 2 mA current source for a differential termination of 100 ohms with no source termination will require a 4 mA current source when using a source termination (for each clock and data channel in a source synchronous implementation).
Many applications do not require the source termination RS, depending upon the required bandwidth and channel quality. However, with increasing data rates and wider adoption of differential I/O technology by consumer electronics manufactures with lower quality communications media due to lower cost implementations (e.g., as compared to industrial and commercial applications) source terminations have become virtually essential. Additionally, the low impendence provided by a source termination improves EMI immunity of the signal interface, since it limits the amount of radiated EMI that can couple into the interface and introduce communication errors. This can be especially important for mobile and handheld applications where EMI immunity is generally of even greater concern.
Referring to FIG. 2, this problem of higher power dissipation in a source terminated LVDS signal link has been addressed with a design proposed by JEDEC (Joint Electron Device Engineering Counsel), which is similar to a static CMOS signal driver with a fixed output impedance of 50 ohms operating on an internally regulated low power supply voltage of 800 mV. The result is this scalable low voltage serial (SLVS) signal link with separate source termination resistances RS1, RS2. Such a design provides power dissipation similar to that of a LVDS signal link without source termination. Scalability is provided in that the power consumption can be further reduced if the internal regulated power supply can be scaled down to 400 mV to reduce the output signal magnitude to 200 mV and signaling current to 2 mA, with further reductions also possible.
However, 4 mA or even 2 mA, per channel, of signaling current results in power dissipation that can still be sufficiently high to make a differential I/O signal interface inefficient for battery-operated applications. Accordingly, additional techniques have been proposed to further reduce power dissipation of a differential I/O signal interface. In one technique, a separate clock channel is made unnecessary by having the clock share one of the data channels or bandwidth, e.g., using clock data recovery (CDR) or other clock embedding techniques. Another technique requires further reduction in the voltage amplitude of the transmitted signal, thereby further reducing the signaling current.
While embedding the clock within a data channel can reduce power dissipation, a phase lock loop (PLL) in the receiver then becomes necessary. Further, the time necessary to acquire and recover the embedded clock signal within the data stream can be long compared to the desired data rate. Moreover, data channel encryption is typically needed to assist the clock data recovery. As a result, with the requirement of a PLL, power dissipation becomes similar to that required by a system using a dedicated clock channel. Meanwhile, a source synchronous link can be powered up quickly with synchronization across the channel established in a simple and reliable manner, with problems arising only at very high data rates (e.g., higher than 3 GB/s per channel) when the skew between the clock and data channels begins to dominate the timing budget of the communications link. Hence, virtually the only advantage of the CDR embedded clock technique is the reduced number of physical connections needed to implement the interface. However, with a sufficient degree of serialization, the difference of an additional two connections to transmit a clock across the link is well within the cost budget for a typical consumer device.
Other than CDR, other techniques have been proposed in which the clock is embedded within the data stream via a logical operation on data channels or some form of pulse with modulation (PWM) of the transmitted signal. However, these techniques often increase complexity of the interface and reduce available bandwidth.
Reducing the signal magnitude, i.e., the voltage swing, can be effective in reducing power dissipation in a differential signal interface. As noted, a conventional LVDS voltage swing is 400 mV, resulting in 4 mA of signal current with no source termination, and 8 mA with source termination. By reducing the voltage swing to 200 mV, these signal currents are reduced to 2 mA and 4 mA, respectively. There have been reports of signal interfaces operating with a 100 mV signal swing, with signal current reduced to 1 mA per channel. However, this results in a reduced signal to noise ratio (SNR) for the interface, thereby producing less reliable operation in the presence of noise. Accordingly, it appears that source termination will be required for a LVDS implementation of a differential I/O link if it is desired to reduce the signal swing to or below 100 mV. As a result, it appears that signal current per channel in such an interface for reliable operation has a minimum of approximately 2 mA. Further, reducing the signal voltage swing causes the performance requirements of the receiver to be increased, since it will now have to distinguish between smaller input differential signals in the presence of voltage offsets, both systematic and random. As a result, offset compensation circuitry may be needed, thereby again increasing circuit complexity.
Accordingly, it would be desirable to have a differential I/O signal interface with reduced power dissipation per channel, low circuit complexity, no inherent bandwidth restrictions, operable without data or clock encoding, operable without imposing additional requirements on the signal receiver, and highly robust resistance to EMI and other noise sources.